Author: Jerry Long, Product Marketing Manager, EMA Design Automation
As technology advances, so do the complexity of the problems it exposes. Nowhere is this
more evident than in high-speed interface design. Timing issues previously deemed
insignificant are now impacting design schedules and can no longer be dealt with after the
fact. Design innovations such as double-data rate memory devices (DDR, DDRII, & DDRIII),
with their source synchronous capabilities and continuing speed improvements, have increased
the impact static timing issues have in resolving high-speed system interface operation.
Margins for data setup and hold requirements are tight which leaves minimal room to secure
an accurate data capture and presentation window. Faster edge rates also magnify physical
design effects, which cause signal integrity issues that require additional settling time, shrinking
timing margins further.
FPGA manufacturers are keeping pace with devices that are extremely register rich and offer
advanced I/O features that directly support these high-speed interface protocols. In addition,
they provide intricate timing control capability with fully programmable phase-locked loop
networks. These features allow design of memory controllers, data exchangers, and pipeline
networks, with full clock/data relationship control, dynamic termination, and I/O technology
networks to comply with the latest interface styles available. While these new advances in FPGA
technology are of tremendous help, they don’t alleviate the importance of static timing, which
if not monitored can render entire designs useless. To take full advantage of these highperformance
features, you still must analyze your available timing options, incorporate signal
integrity and other physical delay effects, and do so throughout the design process.
TimingDesigner® from EMA Design Automation is considered the industry standard timing
analysis tool to aid in complex interface design and development as it provides an easy, selfintuitive
method to address static timing issues using interactive timing diagrams. It is ideal for
high-speed, multi-frequency designs where it is essential to accurately model and analyze
signal relationships between devices on a board or between embedded functions on an ASIC
or FPGA. It can evaluate comprehensive sets of timing alternatives and provide direction to the
most complex of timing challenges, enabling designers to manage and monitor timing
margins throughout the design process. In addition, TimingDesigner can generate place and
route constraints in SDC format that reference design specific
timing measurements, and allows direct use of post place-and-route timing information for
signal delays providing visual verification of the interface signal relationships required for
desired FPGA interface operation.
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