Co Authors: Jerry Long, Product Marketing Manager, EMA Design Automation
Sandy Helton, Principle Engineer, Xilinx Inc.
TimingDesigner from EMA Design Automation
has many powerful features that allow a multitude
of timing and verification issues to be analyzed.
Many companies employ TimingDesigner to aid
in complex interface design and development as
it provides an easy, self-intuitive method to address
static timing issues using timing diagrams. One
such area is complex memory interface design and
control. This paper presents some TimingDesigner
‘use model’ ideas in common use today for
development of Double-Data Rate (DDR) interface
and controller design.
Designing controllers for DDR and/or Quad Data
RateTM (QDRTM) memory devices presents some
very unique timing challenges such as signal
skew analysis and adjustments, and specific
clock generation and control, all to ensure proper
clock/data relationships. Typically DDR style
controllers are implemented in FPGA devices due
to their register-rich architectures, powerful PLL
clock network generators, and memory interface
friendly I/Os, all providing a highly efficient and
flexible (i.e. programmable) environment to
read, write, and process data. These memory
interfaces are typically operating at frequencies
of 200 MHz and higher, presenting non-trivial
timing challenges.
However, the interface timing is not the only
complex issue at hand, there’s also the challenge
of data management and manipulation within
the FPGA fabric. Depending on the nature of the
controller design at hand, the data preparation
phase can be several magnitudes more complex
than data capture. The complexity involves how
to feed data processing units, most of which are
completely independent from one another and
can therefore be operating at different clock rates.
The unique features contained in TimingDesigner
provide an environment for not only deciphering
interface timing, but also allow insight into data
manipulation issues beyond the interface. Using
TimingDesigner in conjunction with an industry
standard HDL based simulator provides a
methodology for functional verification and
debugging of very complex design issues much
faster then simulation environments alone.
TimingDesigner can play a very prominent role
in the identification and resolution of system
operation and control issues, providing very high
observability at a low-level of abstraction.
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