Cadence Allegro PCB Signal Integrity (SI) Interface
TimingDesigner® 9.2 now provides a seamless integration with
Cadence® Allegro® PCB SI to aide in more accurate timing
analysis. Joint signal integrity and timing analysis is becoming
increasingly important as design speeds grow, margins shrink, and
project schedules shorten. This enhanced integration allows users
to import simulated interconnect delays from Allegro PCB SI,
enabling design teams to resolve timing issues early in the design
process when the cost of change is the lowest.
Benefits:
- Accurate analysis through patented TimingDesigner algorithms
combined with Cadence Design Systems signal integrity simulation
technology
- Graphical view of signal integrity affected timing margins makes
it easy to see and repair violations
- Template files enable fast updates of SI results as design
iterations occur
- Flexible timing models supports easy re-use among designs
Generate SDC Timing Constraints
The introduction of version 9.1 made TimingDesigner the only tool
that could generate SDC timing constraints from a timing diagram.
This enabled users to visually define design requirements and then
automatically generate SDC to drive place and route. The latest
TimingDesigner 9.2 release continues this development initiative by
providing better support for multiple SDC variants, SDC management,
and auto-generation of constraint values based on downstream
requirements.
SDC is an open source industry standard timing constraint format
supported by most FPGA and ASIC design flows. Allowing users to generate
SDC constraint files from a timing diagram reduces the complexity of the
SDC constraint format, while providing users a visual verification that
their constraints are specifying the desired design intent.
Benefits:
- Enables users to take advantage of powerful features in the SDC
constraint format without having to learn all the nuances of writing
SDC
- Generates constraints from a diagram description ensuring that
the SDC commands mirror the desired design intent
- Incorporate timing delays and requirements for all components
in the interface, enabling a system level view of timing
- Automatically develops documentation to describe interface
timing requirements
Enhanced Altera TimeQuest Timing Analyzer Interface
With TimingDesigner 9.2 users can import diagram specific delay path
timing data from Altera® TimeQuest Timing Analyzer for analysis and
verification. This allows users to incorporate internal FPGA delays
into their timing analysis to ensure they are meeting their FPGA and
system requirements; providing a platform for final timing signoff
on critical interfaces. This newest release provides support for more
reporting formats, as well as for 65nm and smaller geometry devices.
Actel Libero Interface
Actel® Libero® is an FPGA development environment that supports
SDC. This environment contains a TCL scripting interface which allows
users to generate custom timing reports. TimingDesigner 9.2 comes
installed with an Actel TCL script template which allows a user to run
custom reports in the Libero tool and extract relevant timing delay
data to include in TimingDesigner projects. The TCL file collects delay
information from the Actel tool based on the SDC enabled elements in a
specific timing diagram.
General Usability Enhancements
TimingDesigner 9.2 also includes a number of general productivity
enhancements and updates as part of the ongoing efforts to provide the
highest quality timing analysis software on the market.
Derived Clock - now allows the user to take a clock already present in the design and convert it to a derived clock with a new source picked from a list of clocks in the diagram. This new derived clock will collect characteristics, such as name, direction, port, and objects, from the original clock and pass them to the new derived clock
SDF Import - has been upgraded to present delays in a hierarchical tree format and allow selection of multiple values at once for import. Users can also sort the SDF file for contents to better find and select similar elements
Library Browser - has been enhanced with a more Microsoft® Windows like operation to provide better ease of use
Tree View - enables clearer and easier searching for desired variables, and also helps users understand the hierarchy present in TimingDesigner for allowing variable overrides
Variable Overrides – allows designers to override variables they feel are incorrect for their particular project or diagram, without having to change an original library
Over 200 New Design Kits Available
EMA continues to support the Design Kit program and has made
available over 200 new timing models since the initial release.
The TimingDesigner Design Kits are pre-assembled component
diagrams complete with all specified libraries for speed and
voltage ratings, and are intended to provide designers with a
time saving head start for timing analysis of their designs.
Each kit consists of all documented timing protocols associated
with one or more design components, and are assembled for easy
importation into TimingDesigner’s Manager Window allowing quick
assembly of any timing project. Design Kits are available to all
customers with a valid maintenance contract.
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