The Industry's Most Accurate and Interactive Static Timing Analysis
 
"The new TimingDesigner interface with Cadence Allegro PCB SI allows me to accomplish in 20 minutes what used to take 3 days. Because of this, I have my entire team using TimingDesigner."

- Bryn Holmes,
   Fujitsu Telecommunications Europe Ltd.
   Principal Design Engineer - Hardware Engineering
"GSI Technology is proud to provide our customers with TimingDesigner® models for our SigmaQuad family of SRAM products."

These models will enable customers to:
  • Perform an accurate and detailed timing analysis of SigmaQuad memory interfaces
  • Understand the operation of SigmaQuad devices, allowing for faster design of the SigmaQuad interface
"Altera works closely with the EMA development team to enable a tight, seamless interface between our Quartus II software and TimingDesigner. As a result of this effort, customers can leverage the graphical timing analysis features of TimingDesigner to rapidly develop their SDC timing constraints for Altera devices."
  • - Chris Balough, Altera Corporation
       Senior Director of Software
"After realizing the value that is gained by using TimingDesigner in our own internal development environment, it was a natural progression to see the benefits Simtek customers can realize with TimingDesigner and interactive timing models of our devices."
  • - Grant Hulse, Simtek Corporation
       Vice President of Worldwide Marketing
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Static Timing Analysis with TimingDesigner
Static Timing Analysis
Try TimingDesigner the interactive timing analysis tool for high speed, multi-frequency designs. More >
New Applicate Note:
Using TimingDesigner to Generate SDC Timing Constraints More >
Rochester, NY (August 31, 2010) EMA Announces TimingDesigner 9.25 - EMA today announced TimingDesigner® 9.25, which features automated interface analysis capabilities designed to save valuable design time while still ensuring thorough and accurate timing analysis. More >
Simulation and Timing for Signal Integrity Webinar, December 10th - Join EMA for a free webinar on how to take simulation timing data and determine timing margins for signal integrity analysis. An example timing walk through will be shown featuring TimingDesigner 9.2. More >
Rochester, NY (August 19, 2009) EMA Announces TimingDesigner 9.2 - EMA today announced the release of TimingDesigner 9.2 featuring a new interface to Cadence® Allegro® PCB SI technology.   More >
San Jose, CA (Feb. 24 – Feb. 25 2009) DVCon Expo - Vendors display the latest in Hardware Description Languages, Hardware Verification Languages and EDA tools for the design and verification of electronic systems and integrated circuits. Visit EMA in booth 504 and enter to win a free one-year license of TimingDesigner.  More >
Rochester, NY (October 21, 2008) EMA Announces TimingDesigner 9.1 - EMA today announced the release of TimingDesigner 9.1 featuring SDC support and integration with Altera’s Quartus II Software. This enables users to visually define design requirements and then automatically generate SDC to drive place and route. More >