Articles
Control Your QDR Designs
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
This article describes how to solve QDR memory data capture challenges with Xilinx Virtex-II FPGAs.
Published: Fall 2004 in Xilinx Xcell Journal.
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Get Control of Your High-Speed Designs
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
This article describes how Chronology and Xilinx have teamed up to solve timing challenges associated with high-speed memory interface designs.
Published: Winter 2002 in Xilinx Xcell Journal.
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Whitepapers and Application Notes
Using TimingDesigner with the Altera Design Flow
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
TimingDesigner® brings graphical interface timing analysis to Altera® through new
SDC generation and TimeQuest integration. This application note shows how you can easily
constrain and analyze your FPGA interfaces.
Published: Fall 2008 CircuiTree Magazine
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Using TimingDesigner to Generate SDC Timing Constraints
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
This article describes how to generate SDC for development of FPGA designs.
Published: Fall 2008 CircuiTree Magazine
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Develop State Machine Architecture for Complex Interfaces
Co Authors: Jerry Long, Product Marketing Manager, EMA Design Automation
Sandy Helton, Principle Engineer, Xilinx Inc.
Use TimingDesigner to Develop State Machine (Event Driven) Architecture for Complex interfaces.
Learn how to use derived signal features, perform waveform ‘value decode’, and validate input
equation alterations with your HDL of choice.
Released: April 2008
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How To Effectively Manage Timing of FPGA Design Flows
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
Designing FPGAs with the high-speed interface technologies available today helps you meet market
demands, but it also presents some interesting design challenges.
Last Edited: April 2007
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