The Industry's Most Accurate and Interactive Static Timing Analysis
Home > Resources > Articles and Whitepapers
TimingDesigner

TimingDesigner articles and whitepapers

TimingDesigner Demo  View TimingDesigner Demo
 

TimingDesigner

TimingDesigner Articles and Whitepapers
  Printer friendly version of this page

Articles

Control Your QDR Designs
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
This article describes how to solve QDR memory data capture challenges with Xilinx Virtex-II FPGAs.
Published: Fall 2004 in Xilinx Xcell Journal.
Download now

Get Control of Your High-Speed Designs
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
This article describes how Chronology and Xilinx have teamed up to solve timing challenges associated with high-speed memory interface designs.
Published: Winter 2002 in Xilinx Xcell Journal.
Download now



Whitepapers and Application Notes

TimingDesigner and Cadence Allegro PCB SI Interface
Author: Chris Banton, Product Marketing Manager, EMA Design Automation
TimingDesigner® 9.2 now provides integration with Allegro PCB SI to aide in more accurate timing analysis. This application note provides extended details on this integration.
Released: Winter 2010
View Sample | Download Entire Application Note | Download Application Note w/ Sample Files

Using TimingDesigner with the Altera Design Flow
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
TimingDesigner brings graphical interface timing analysis to Altera® through new SDC generation and TimeQuest integration. This application note shows how you can easily constrain and analyze your FPGA interfaces.
Published: Fall 2008 CircuiTree Magazine
View Sample | Download Entire Application Note | Download Application Note w/ Sample Files

Using TimingDesigner to Generate SDC Timing Constraints
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
This article describes how to generate SDC for development of FPGA designs.
Published: Fall 2008 CircuiTree Magazine
View Sample | Download Entire Application Note

Develop State Machine Architecture for Complex Interfaces
Co Authors: Jerry Long, Product Marketing Manager, EMA Design Automation
Sandy Helton, Principle Engineer, Xilinx Inc.
Use TimingDesigner to Develop State Machine (Event Driven) Architecture for Complex interfaces. Learn how to use derived signal features, perform waveform ‘value decode’, and validate input equation alterations with your HDL of choice.
Released: April 2008
View Sample | Download Entire Article

How To Effectively Manage Timing of FPGA Design Flows
Author: Jerry Long, Product Marketing Manager, EMA Design Automation
Designing FPGAs with the high-speed interface technologies available today helps you meet market demands, but it also presents some interesting design challenges.
Last Edited: April 2007
View Sample | Download Entire Article