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TimingDesigner

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EMA iTrain Online provides a self-paced, online eLearning solution. The “Timing Analysis with TimingDesigner®” iTrain course teaches timing analysis concepts and skills through a hands-on learning process, with laboratory exercises to quickly boost your confidence and productivity. Live technical support is available to answer questions as they arise, and participants can evaluate their progress in a special “Test Your Knowledge” section.

Timing Analysis with TimingDesigner
The “Timing Analysis with TimingDesigner” iTrain course is designed to augment the TimingDesigner Quick Start Training Guide, and uses the tutorial included with the TimingDesigner User's Guide as a starting point, expanding that learning experience into six Lab Lessons. Users will find this thorough training includes the next level of detail to advance their use of TimingDesigner.

These labs serve to teach the basics of creating a timing diagram with TimingDesigner, as well as teaching advanced analysis capabilities that go beyond the scope of the tutorial.

TimingDesigner allows creation of timing diagrams for many purposes, such as capturing interface specifications, communicating design requirements, publishing component specifications, and analyzing timing at the interfaces between component or module blocks. This lab training is broken into several labs to highlight these purposes.

Lab 1: Creating timing diagrams and an interface protocol specification - Covers the basic steps involved in creating timing diagrams and interface specifications. The user will create a clock, several signals, add edges to the signals, add delays, and add constraints for setup and hold time requirements.

Lab 2: Using the Parameter and Library Spreadsheets - Covers basic use of the parameter and library windows. The user will manipulate their design from the parameter window and utilize the standard built-in timing libraries that are provided with TimingDesigner to perform simple timing analysis including parts substitution, use of variables and formulas.

Lab 3: Adding documentation aids for publishing - Covers a number of features that are helpful for document publishing. In this lab, the user will add two cycle bars, add labels to edges/states, add descriptive text in a footer, add descriptive text for a signal edge, and work with diagram styles.

Lab 4: Using Derived Signals and Derived Clocks - Covers the application of Derived Clocks and Derived Signals in your diagrams. The user will use Derived Signals to model a parity line and an enabled counter using the conditional operator. The user will use a Derived Clock to model a PLL circuit, and use variables and formulas to model jitter introduced on the PLL clock.

Lab 5: Advanced timing analysis - In this lab the user will use what they've learned so far to analyze the connection between an Intel 186 and a Micron DRAM. The user will look for timing problems and perform some what-if analysis.

Lab 6: Other advanced concepts - This lab demonstrates methods of exporting, importing, and using the command line interface and TimingDesigner's "Batch Mode" to modify timing diagram styles.