The Industry's Most Accurate and Interactive Static Timing Analysis
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TimingDesigner

TimingDesigner 9.1 features include the ability to create SDC timing constraints

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TimingDesigner
TimingDesigner 9.25
The industry’s most accurate and interactive static timing analysis

TimingDesigner® release 9.25 brings a host of enhancements to the engineers timing analysis flow. These enhancements provide users with significant productivity improvements helping design teams quickly and accurately define and analyze their critical interface timing faster than ever before.

Enhanced AutoMerge Flow

Release 9.25 provides an enhanced flow for automatically creating an interface timing analysis based on component timing models. This provide a re-usable model based approach to a user’s timing analysis, greatly reducing the time required to move from inputting timing data to a functional timing analysis.

Benefits include:
  • Automated process that saves time and reduces errors
  • Automatic setup for easy what-if analysis
  • Model based flow that promotes re-use
  • Easy import of interconnect delay factors, such as signal integrity results and propagation delays, providing highly accurate timing margin calculations


Signal Integrity Timing Imports

Accurate interface timing analysis requires detailed information on all pieces of the interface (components and interconnects). With today’s high-speed interfaces, signal integrity effects can have a significant impact on timing margins. Release 9.25 expands TimingDesigner import capabilities from the previous release to provide import support for more signal integrity file formats.

Benefits of this feature include:
  • Patented TimingDesigner algorithms combined with simulated signal integrity delays provides a full flow for accurate interface timing validation
  • Graphical view of signal integrity affected timing margins makes it easy to see and repair violations
  • Flexible solution supports easy design reuse
  • Graphical timing models allows for additional protocol level analysis like bus contention checks which are needed to fully validate the design before production.



Diagram Tracking and Verification Tools

Release 9.25 provides features to help track edits and verify your diagrams are being developed properly.. This is especially important in today’s distributed design teams, as diagrams are shared, reviewed, and updated by many users throughout the organization who may not have been involved in the original development of the analysis.

New capabilities include:
  • Tracking last save and export: Enables design teams to easily monitor when the diagram was last edited to ensure documentation is in synch with the latest diagram files.
  • Identify critical constraint(s): Allows users to quickly identify the limiting path in their design to focus for analysis and optimization
  • Identify error event(s): Ensures diagrams are set up properly and users are not receiving false results due to incorrect library paths or formulas.


Operating System Support

TimingDesigner 9.25 provides support for Windows 7 and Red Hat Enterprise Linux (RHEL) 5.

Availability:

TimingDesigner 9.25 will be available for customers on active maintenance in the middle of September 2010. You will receive notification of availability and link to download. Off maintenance users should contact EMA at 877.362.3321 or info@ema-eda.com to learn how to access the new version.

More Information:

TimingDesigner is manufactured and supported by EMA Design Automation. For further questions on TimingDesigner or to find your local reseller, please visit our TimingDesigner page or follow the steps below:

Call 800.813.7494 Call 877.362.3321 • Send us an e-mail

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